Circuit failures, such as Static Random Access Memory (SRAM) cell instability fails in a large memory array, arising from statistical fluctuations in Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) parameters, or hard fails, from Back End of Line (BEOL) shorts and opens, directly impact both the yield and reliability of Complementary Metal Oxide Semiconductor (CMOS) products. MOSFET characteristics of a few devices (typically ten to twenty) are measured in the manufacturing line to monitor process variations, but provide little information on statistical variations. Test time and subsequently cost limitations preclude the measurements of a large array of field effect transistors (FETs) in-line. Process yield monitors use large memory arrays however array failures do not directly provide information on the individual MOSFET (Positive-Channel Metal Oxide Semiconductor (PMOS) and Negative-Channel Metal Oxide Semiconductor (NMOS)) components. BEOL yield monitors are used to provide information on random opens and shorts, with localization possible at the cost of design complexity. Memory array yield monitors and BEOL yield monitors that provide localization require external clocks using expensive test equipment with relatively long test times.
There is a need in the art for test structures that can rapidly provide statistical information on properties of a large number of devices as well as identification of random opens and shorts, all with localization, using only direct current (DC) inputs and standard in-line test equipment.